The present invention relates generally to post-silicon validation processes, and more particularly to improving efficiency of cycle-reproducible debug processes in a multi-core environment.
A post-silicon validation process can comprise four interleaved elements: stimulating a design under test (DUT), detecting erroneous behavior within the DUT, localizing a root cause of the erroneous behavior, and providing a fix.
The first two elements of the post-silicon validation process, i.e., stimuli generation and error detection, may be addressed through the use of bare-metal hardware exercisers, sometimes called software-based self-testing. Exercisers may be programs that run on a DUT, where the exercisers generate one or more test cases, execute the one or more test cases, and evaluate results from one or more test cases.
A debugging fail may be used to determine the root cause of an error by repeatedly executing a fail test in a cycle-reproducible environment to collect cycle-by-cycle latch data to create a multi-cycle trace of a chiplet's various latch states. This debug method relies on a design's reproducibility behavior within chiplet bounds and functions that enable executing the design for a given number of cycles. Typically, gathering a multi-cycle trace from the cycle-reproducible environment is performed using a single core.